The present invention relates to an inter-bus control circuit for relaying a plurality of extended buses in a small computer such as a personal computer and to a computer system having the control circuit.
In recent years, personal computers have been becoming remarkably popular, and significant changes have been made to extended buses for communicating information between a CPU and a variety of input/output devices and improvements have been gained in performance of the CPU. Conventionally, a standard called the ISA (Industry Standard Architecture) bus has been generally adopted as for the extended bus used in personal computers. Thus, a variety of expansion boards based on this standard have been made commercially available in the market.
While faster processing of the CPU has been accomplished by the improved performance of the CPU, the data transfer speed between a CPU and an input/output device has not so increased as long as the ISA bus is employed. It is therefore necessary to employ a faster extended bus in order to improve the processing performance of an entire system.
A standard for such a faster extended bus recently drawing attention is a bus standard called PCI (Peripheral Component Interconnection) which has been established as a standard with Intel Corporation, U.S.A., as the leader.
The PCI bus has advantages as compared with the ISA bus because of in a faster data transfer capability, a resource collision avoidance capability provided by an automatic relocation mechanism of a memory space, an I/O space by configuration functions, and so on, so that it is highly possible that the PCI bus will be adopted in the future as an input/output bus for high performance small computers such as work stations as well as personal computers.
The PCI bus standard defines an upper limit to the number of devices and expansion slots connected to a bus in order to prevent erroneous operations possibly due to deteriorated electrical characteristics caused by a high operating frequency. Thus, a plurality of PCI buses must be configured for providing a system with a number of devices and expansion slots in order to exceed the upper limit. As an approach for configuring a plurality of PCI buses, "PCI to PCI Bridge Architecture Specification" has been proposed by PCISIG.
This proposal describes a guideline about a control scheme for a bridge circuit for relaying a first PCI bus (primary bus) and a second PCI bus (secondary bus) when a plurality of PCI buses are configured. A similar technique is also described in detail in a data book for a PCI-PCI bridge chip, "DEC chip 21050 PCI-to-PCI Bridge Data Sheet", pp 1-3-1-5, published by Digital Equipment Corporation.
FIGS. 2A and 2B illustrate a conventional computer system having a double bus configuration and a conventional PCI-PCI bridge, respectively. In FIG. 2A, the system comprises a CPU 1; a memory 2; a bus/memory controller 3 for performing a conversion from a local bus 100 of the CPU 1 (hereinafter called the "processor bus") to a first PCI bus 200, an access control of the memory 2, and so on; a PCI-PCI bridge circuit (1) 4 for relaying the first PCI bus 200 and a second PCI bus 201; and another PCI-PCI bridge circuit (2) 5 for relaying the second PCI bus 201 and a third PCI bus 202. PCI devices for controlling a variety of input/output devices are connected to the respective PCI buses.
For example, a configuration assumed here may be such that PCI devices 6, 7 connected to the first PCI bus 200 are controllers for controlling a display and a file storage unit (though not illustrated), and PCI devices 8, 9 connected to the third PCI bus 202 may be controllers for controlling a communication network. The PCI-PCI bridge circuit 2 (5) and the PCI devices 8, 9 are connected to the second PCI bus 201 through a connector 10.
In this way, the connection between the processor bus 100 and the plurality of PCI buses 200-202 is realized in a hierarchical configuration. It should be noted that, although not: illustrated, commercially available controllers and expansion boards for the ISA bus may also be used in the system of FIG. 2A through a PCI-ISA bridge circuit for the conversion between the PCI bus and the conventional ISA bus.
Each of these bridge circuits are generally composed of one or a plurality of LSI's.
The PCI- PCI bridge circuits 4, 5 are actually implemented by the same LSI which has an internal configuration as illustrated in FIG. 2B. More specifically, a portion for interfacing with the first PCI bus (primary bus) is connected to a primary target unit 41 and a primary master unit 43, while a portion for interfacing the second PCI bus (secondary bus) is connected to a secondary master unit 42 and a secondary target unit 44.
Further, the PCI-PCI bridge circuit includes a configuration register 45 for setting a PCI space and so on based on the PCI bus standard, a data buffer used for receiving and passing bus cycles of both buses, and so on.
When a device connected to the secondary bus is accessed by a device connected to the primary bus (for example, the bus/memory controller 3), the primary target unit 41 in the PCI-PCI bridge circuit 4 receives the access and passes it to the secondary master unit 42 which in turn generates a bus cycle as an access on the secondary bus.
Similarly, when a device connected to the primary bus is accessed by a device connected to the secondary bus, the secondary target unit 44 in the PCI-PCI bridge circuit 4 receives the access and passes it to the primary master unit 43 which in turn generates a bus cycle as an access on the primary bus.
In this way, since a plurality of PCI buses can be configured in a single system through the PCI-PCI bridge circuit performing the relay function, the system can be provided with a larger number of PCI devices and expansion slots.
However, the foregoing PCI-PCI bridge circuit merely receives and passes accesses between the first PCI bus and the second PCI bus. More specifically, the PCI-PCI bridge circuit merely receives a bus cycle generated on one bus as a target and generates a bus cycle as a bus master on the other bus.
With this configuration, the second PCI bus must be provided with dedicated control circuits connected thereto, each for incorporating a memory control mechanism common to devices connected to the second PCI bus, an inter-processor interrupt control mechanism required when a plurality of local processors are connected thereto, and so on. Thus, the respective control circuits will have their own circuits for decoding a bus cycle and so on, so that the scale of logical gates is increased in the entire configuration. Also, since the respective control circuits are formed of separate integrated circuits, the number of parts and an area required to mount these parts on a board are also increased. Thus, the conventional PCI-PCI bridge circuit has a problem in that the number of parts and required substrate area is increased, resulting in the need for larger expansion cards and consequently an increased cost of the entire system.